x86: Remove timeouts from INIT-SIPI-SIPI sequence when using x2apic.

Some of the timeouts are pointless since they're waiting for the ICR
to ack the IPI delivery and that doesn't happen on x2apic.
The others should be benign (and are suggested in the SDM) but
removing them makes AP bringup much more reliable on some test boxes.

Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>

diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index c38398cf54f8d4142a9bade07f9689e178cfd29c..7f0093bc08c3d84f7f79311bba4dab29078e04a6 100644 (file)
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -436,29 +436,30 @@ static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
     apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
                    phys_apicid);
 
-    Dprintk("Waiting for send to finish...\n");
-    timeout = 0;
-    do {
-        Dprintk("+");
-        udelay(100);
-        if ( !x2apic_enabled )
+    if ( !x2apic_enabled )
+    {
+        Dprintk("Waiting for send to finish...\n");
+        timeout = 0;
+        do {
+            Dprintk("+");
+            udelay(100);
             send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-    } while ( send_status && (timeout++ < 1000) );
+        } while ( send_status && (timeout++ < 1000) );
 
-    mdelay(10);
+        mdelay(10);
 
-    Dprintk("Deasserting INIT.\n");
+        Dprintk("Deasserting INIT.\n");
 
-    apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
+        apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 
-    Dprintk("Waiting for send to finish...\n");
-    timeout = 0;
-    do {
-        Dprintk("+");
-        udelay(100);
-        if ( !x2apic_enabled )
+        Dprintk("Waiting for send to finish...\n");
+        timeout = 0;
+        do {
+            Dprintk("+");
+            udelay(100);
             send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-    } while ( send_status && (timeout++ < 1000) );
+        } while ( send_status && (timeout++ < 1000) );
+    }
 
     /*
      * Should we send STARTUP IPIs ?
@@ -487,22 +488,24 @@ static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
          */
         apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid);
 
-        /* Give the other CPU some time to accept the IPI. */
-        udelay(300);
+        if ( !x2apic_enabled )
+        {
+            /* Give the other CPU some time to accept the IPI. */
+            udelay(300);
 
-        Dprintk("Startup point 1.\n");
+            Dprintk("Startup point 1.\n");
 
-        Dprintk("Waiting for send to finish...\n");
-        timeout = 0;
-        do {
-            Dprintk("+");
-            udelay(100);
-            if ( !x2apic_enabled )
-            send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-        } while ( send_status && (timeout++ < 1000) );
+            Dprintk("Waiting for send to finish...\n");
+            timeout = 0;
+            do {
+                Dprintk("+");
+                udelay(100);
+                send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
+            } while ( send_status && (timeout++ < 1000) );
 
-        /* Give the other CPU some time to accept the IPI. */
-        udelay(200);
+            /* Give the other CPU some time to accept the IPI. */
+            udelay(200);
+        }
 
         /* Due to the Pentium erratum 3AP. */
         if ( maxlvt > 3 )